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1-TO-1 2.5V, 3.3V DIFFERENTIAL-TOLVCMOS/LVTTL TRANSLATOR General Description
ICS830S21I is a 1-to-1 Differential-to- LVCMOS/ LVTTL translator and a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from IDT. The differential input is highly flexible and can accept the following input types: LVPECL, LVDS, LVHSTL, SSTL and HCSL. The small 8-lead SOIC footprint makes this device ideal for use in applications with limited board space.
ICS830S21I Features
* * * * * * * * * *
One LVCMOS/LVTTL output Differential CLK, nCLK input pair CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL Maximum output frequency: 350MHz Part-to-part skew: 525ps (maximum) Additive Phase jitter, RMS: 0.11ps (typical) Small 8 lead SOIC package saves board space Full 3.3V and 2.5V operating supply -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package
ICS
Block Diagram
CLK Pullup/Pulldown Q nCLK Pullup/Pulldown VBB
Pin Assignment
nc CLK nCLK VBB 1 2 3 4 8 7 6 5 VDD Q nc GND
ICS830S21I 8-Lead SOIC 3.9mm x 4.9mm x 1.375mm package body M Package Top View
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ICS830S21AMI REV. A MARCH 21, 2008
ICS830S21I 1-TO-1, 2.5V, 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR
Table 1. Pin Descriptions
Number 1, 6 2 3 4 5 7 8 Name nc CLK nCLK VBB GND Q VDD Unused Input Input Output Power Output Power Pullup/ Pulldown Pullup/ Pulldown Type Description No connect. Non-inverting differential clock input. Inverting differential clock input. Output reference voltage. Power supply ground. Single-ended clock output. LVCMOS / LVTTL interface levels. Positive supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol CIN RPULLUP RPULLDOWN CPD Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance VDD = 3.465V VDD = 2.625V Output Impedance VDD = 3.3V VDD = 2.5V Test Conditions Minimum Typical 4 51 51 10 8 10 12 Maximum Units pF k k pF pF
ROUT

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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG Rating 4.6V -0.5V to VDD + 0.5V -0.5V to VDD + 0.5V 93.1C/W (0 mps) -65C to 150C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics, VDD = 3.3V 5%, TA = -40C to 85C
Symbol VDD IDD Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 12 Units V mA
Table 3B. Power Supply DC Characteristics, VDD = 2.5V 5%, TA = -40C to 85C
Symbol VDD IDD Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 2.375 Typical 2.5 Maximum 2.625 11 Units V mA
Table 3C. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V 5% or 2.5V 5%, TA = -40C to 85C
Symbol VOH VOL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Test Conditions VDD = 3.3V VDD = 2.5V VDD = 3.3V or 2.5V Minimum 2.6 1.8 0.5 Typical Maximum Units V V V
NOTE 1: Outputs terminated with 50 to VDD/2. See Parameter Measurement Information, Output Load Test Circuit diagrams.
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Table 3D. Differential DC Characteristics, VDD = 3.3V 5% or 2.5V 5%, TA = -40C to 85C
Symbol IIH IIL VPP VCMR VBB Parameter Input High Current Input Low Current Peak-to-Peak Voltage; NOTE 1 Common Mode Input Voltage; NOTE 1, 2 Output Voltage Reference Test Conditions VDD = VIN = 3.465V or 2.625V VDD = 3.465V or 2.625V, VIN = 0V -150 0.15 GND + 0.5 VDD - 1.4 VDD - 1.3 1.5 VDD - 0.85 VDD - 1.2 Minimum Typical Maximum 150 Units A A V V V
NOTE 1:VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH.
AC Electrical Characteristics
Table 4A. AC Characteristics, VDD = 3.3V 5%, TA = -40C to 85C
Parameter fMAX tPD tsk(pp) tjit tR / tF odc Symbol Output Frequency Propagation Delay, NOTE 1 Part-to-Part Skew; NOTE 2, 3 Buffer Additive Phase jitter, RMS; refer to Additive Phase Jitter Section Output Rise/Fall Time Output Duty Cycle 350MHz, Integration Range (12kHz - 20MHz) 20% to 80% 266MHz 85 47 0.11 0.95 Test Conditions Minimum Typical 350 1.95 525 1 500 53 Maximum Units MHz ns ps ps ps %
NOTE 1: Measured from the differential input crossing point to the output at VDD/2. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the same type of input on each device, the output is measured at VDD/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Table 4B. AC Characteristics, VDD = 2.5V 5%, TA = -40C to 85C
Parameter fMAX tPD tsk(pp) tjit tR / tF odc Symbol Output Frequency Propagation Delay, NOTE 1 Part-to-Part Skew; NOTE 2, 3 Buffer Additive Phase jitter, RMS; refer to Additive Phase Jitter Section Output Rise/Fall Time Output Duty Cycle 350MHz, Integration Range (12kHz - 20MHz) 20% to 80% 266MHz 125 47 0.11 1 Test Conditions Minimum Typical 350 2 550 1 500 53 Maximum Units MHz ns ps ps ps %
NOTE 1: Measured from the differential input crossing point to the output at VDD/2. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the same type of input on each device, the output is measured at VDD/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 350MHz 12kHz to 20MHz = 0.11ps (typical)
SSB Phase Noise dBc/Hz
Offset Frequency (Hz) As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment.
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Parameter Measurement Information
1.65V5% 1.25V5%
VDD
SCOPE
Qx
VDD
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
-1.65V5%
-1.25V5%
3.3V Core/3.3V LVCMOS Output Load AC Test Circuit
2.5V Core/2.5V LVCMOS Output Load AC Test Circuit
VDD nCLK nCLK
V
PP
CLK
Cross Points V
CMR
CLK Q GND
VDD 2 t
PD
Differential Input Level
Propagation Delay
V
Q
DD
2
80% 20% tR
80% 20% tF
t PW
t
PERIOD
Q
odc =
t PW t PERIOD
x 100%
Output Duty Cycle/Pulse Width/Period
Output Rise/Fall Time
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ICS830S21I 1-TO-1, 2.5V, 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR
Parameter Measurement Information, continued
Par t 1 V
Qx
DD
2 Par t 2 V
DD
Qy
2 tsk(pp)
Part-to-Part Skew
Application Information
Wiring the Differential Input to Accept Single Ended Levels
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input CLK
V_REF nCLK C1 0.1u
R2 1K
Figure 1. Single-Ended Signal Driving Differential Input
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Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 2A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
3.3V 3.3V 1.8V Zo = 50 Zo = 50 CLK Zo = 50 Zo = 50 nCLK nCLK CLK 3.3V
LVPECL HiPerClockS Input
R1 50 R2 50
HiPerClockS Input
LVHSTL IDT HiPerClockS LVHSTL Driver
R1 50 R2 50
R2 50
Figure 2A. HiPerClockS CLK/nCLK Input Driven by an IDT Open Emitter HiPerClockS LVHSTL Driver
Figure 2B. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver
3.3V 3.3V 3.3V R3 125 Zo = 50 CLK CLK Zo = 50 nCLK R1 100 R4 125 3.3V 3.3V Zo = 50
LVPECL
R1 84 R2 84
HiPerClockS Input
Zo = 50
nCLK
LVDS
Receiver
Figure 2C. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver
Figure 2D. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVDS Driver
2.5V 3.3V 2.5V R3 120 Zo = 60 R4 120
2.5V
3.3V
*R3
33
Zo = 50 CLK Zo = 50 nCLK Zo = 60
CLK
nCLK
HCSL
*R4
33 R1 50 R2 50
HiPerClockS Input
SSTL
R1 120 R2 120
HiPerClockS
*Optional - R3 and R4 can be 0
Figure 2E. HiPerClockS CLK/nCLK Input Driven by a 3.3V HCSL Driver
Figure 2F. HiPerClockS CLK/nCLK Input Driven by a 2.5V SSTL Driver
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Reliability Information
Table 5. JA vs. Air Flow Table for a 8 Lead SOIC
JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 93.1C/W 1 84.3C/W 2.5 79.6C/W
Transistor Count
The transistor count for ICS830S21I is: 214
Package Outline and Package Dimensions
Package Outline - M Suffix for 8 Lead SOIC Table 6. Package Dimensions
All Dimensions in Millimeters Symbol Minimum Maximum N 8 A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e 1.27 Basic H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 0 8 Reference Document: JEDEC Publication 95, MS-012
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Ordering Information
Table 7. Ordering Information
Part/Order Number 830S21AMILF 830S21AMILFT Marking 30S21AIL 30S21AIL Package "Lead-Free" 8 Lead SOIC "Lead-Free" 8 Lead SOIC Shipping Packaging Tube 2500 Tape & Reel Temperature -40C to 85C -40C to 85C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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